The present invention relates to persistent memory, and more specifically, to maintaining the consistency of data stored in persistent memory by separating the committing and hardening of data in volatile caches.
Persistent main memory preserves its contents in the absence of power, whereas conventional dynamic random-access memory and processor caches are volatile memories which lose their contents in the absence of power. Consistency means that the memory operations are ordered and atomic even in the event of a mid-operation power failure. A program running on a central processing unit (CPU) expects that its writes to the memory is made persistent in the same order as the write order, and that a data object being written is made persistent either as a whole or not made persistent at all.
With the emergence of persistent main memory, in memory data structures can be treated as persistent at even the object granularity. Moreover, the nonvolatility of data stored in persistent memory can provide advantages over contemporary dynamic random-access memory (DRAM) such as higher capacity, lower cost, and access to persistent storage. However, a challenge in integrating persistent memory technologies with a contemporary memory hierarchy arises because lower levels of the memory hierarchy, such as various levels of caches, are non-persistent and volatile.